1. Field of the Invention
The present invention relates to design of integrated circuits (ICs), and in particular, to implementation of engineering change orders (ECOs) in the IC design process.
2. Description of the Related Art
The design of an integrated circuit (IC) is a complex, lengthy, multi-step process performed with the aid of computers. Electronic design automation (EDA) tools are software tools used in the design of ICs. EDA tools are used to create, test, and edit the high-level design of an IC and then transform the resultant high-level design into a netlist layout for the physical components and their connections. The physical components and their connections will then be etched into a semiconductor substrate to make a physical IC device.
A typical design flow includes the generation of a register transfer level (RTL) design, which defines the IC's functions, such as signal flows or data transfers, at a high level. The RTL design is described using a hardware description language (HDL). A logic synthesis tool, such as the Design Compiler tool from Synopsis, Inc., of Mountain View, Calif., transforms an RTL design for an IC described with an HDL into a netlist for that IC. The netlist describes the logic gates of the IC and their interconnections. A place-and-route tool is then used to arrange the placement of the gates and their interconnections within the IC floorplan. The place-and-route tool generates a placed and routed netlist, which is used to generate masks that define the physical components and their connections. The masks are then used to etch semiconductor wafers to generate physical instances of the IC.
As ICs can be quite complex, and some interactions among components may not be foreseen at early design stages, or requirements may change, it sometimes becomes necessary to modify the RTL design after a placed and routed netlist has already been generated. One way to implement the changes is to modify the RTL according to the new requirements and go through the entire design flow to get a new placed and routed netlist. The placed and routed netlist is then processed to generate a placed and routed database, which includes netlist information, as well as physical dimension information about the cells in the netlist and their interconnections. However, going through the entire design workflow anew can be time-consuming and costly. Furthermore, the normal process flow can be unpredictable and chaotic, wherein small changes to the input may cause large differences in the output. A more efficient system and method for implementing netlist changes would be desirable.